gitlab.telecom-paris.fr / sen 7 Repositories
Dépôts du groupe SEN
sen/dev-projects/rtl-ator
Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
Last synced at: 7 months ago - Stars: 1 - Forks: 0
sen/docs_template
Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).
Last synced at: 7 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0
sen/dev-projects/cfglut5-sbox
16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive
Last synced at: 7 months ago - Stars: 0 - Forks: 0
sen/dev-projects/sv_sim_uart
SystemVerilog simulation environment for an UART
Last synced at: 7 months ago - Stars: 0 - Forks: 0