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gitlab.telecom-paris.fr / sen / dev-projects / rtl-ator

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

JSON API: https://data.code.gouv.fr/api/v1/hosts/gitlab.telecom-paris.fr/repositories/sen%2Fdev-projects%2Frtl-ator

Stars: 1
Forks: 0
Open issues:

License: None
Language:
Dependencies parsed at: Pending

Created at: about 9 years ago
Updated at: over 4 years ago
Last synced at: about 2 years ago

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