gitlab.telecom-paris.fr / sen / dev-projects
sen/dev-projects/cfglut5-sbox
16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive
Last synced at: 7 months ago - Stars: 0 - Forks: 0
sen/dev-projects/sv_sim_uart
SystemVerilog simulation environment for an UART
Last synced at: 7 months ago - Stars: 0 - Forks: 0
sen/dev-projects/rtl-ator
Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
Last synced at: 7 months ago - Stars: 1 - Forks: 0